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src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/Mux.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
    #The base class constructor, with the output from the muxes tree set to be the input
    Actor.Actor.__init__(self,self.muxes_signal_real[0],self.muxes_signal_imag[0],self.muxes_signal_trigger[0],self.muxes_signal_enable[0],no_inputs,output_line_real,output_line_imag,output_trigger,output_enable,no_outputs,input_bitsize=input_bitsize,output_bitsize=output_bitsize,reset=reset,clk=clk)
 
    self.no_input_lines = no_input_lines #Internal variables

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/DivideAndConquer.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
    """
    Actor.Actor.__init__(self,input_line_real,input_line_imag,input_trigger,input_enable,no_inputs,output_line_real,output_line_imag,output_trigger,output_enable,no_outputs,input_bitsize=input_bitsize,output_bitsize=output_bitsize,reset=reset,clk=clk)#,verbosity=verbosity)
 
    self.no_outputs_2 = no_outputs_2

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/Unscrambler.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
    """
    Actor.Actor.__init__(self,input_line_real,input_line_imag,input_trigger,input_enable,no_inputs,output_line_real,output_line_imag,output_trigger,output_enable,no_outputs,input_bitsize=input_bitsize,output_bitsize=output_bitsize,clk=clk,reset=reset) #Call to base Actor class
 
    if(self.input_bitsize): 

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/HDFT.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
    """
    Actor.Actor.__init__(self,input_line_real,input_line_imag,input_trigger,input_enable,no_inputs,output_line_real,output_line_imag,output_trigger,output_enable,no_outputs,reset,clk,input_bitsize,output_bitsize)
 
    self.twiddle_bitsize = twiddle_bitsize

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/DFT.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
    """
    Actor.Actor.__init__(self,input_line_real,input_line_imag,input_trigger,input_enable,no_inputs,output_line_real,output_line_imag,output_trigger,output_enable,no_outputs,reset,clk,input_bitsize,output_bitsize) #Call to base class constructor
 
    self.multiplier_bitsize = multiplier_bitsize

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/HDFT/Reorderer.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
    def __init__(self,clk,input_a,output_a,indices,scale=1):
        Actor.Actor.__init__(self,clk,input_a,output_a,scale)
 
        self.indices = indices
 

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/HDFT/Pipeline_Mux.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
    def __init__(self, clk, input_a, output_a, scale=1):
        Actor.Actor.__init__(self, clk, input_a, output_a, scale)
 
        self.input_line_no = Signal(intbv(0,min=0,max=len(input_a)))
 

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/HDFT/DFT.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
    def __init__(self,clk,input_a,output_a,tf_real,tf_imag,twiddle_bits,scale=1):
        Actor.Actor.__init__(self,clk,input_a,output_a,scale)
 
        self.twiddle_bits = twiddle_bits
        self.twiddle_factors_real = [Signal(intbv(0,min=-2**(self.twiddle_bits-1),max=2**(self.twiddle_bits-1))) for i in range(self.output_a.no_inputs*self.output_a.no_inputs)]

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/HDFT/Butterfly.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
    def __init__(self,clk,input_a,output_a,output_b,tf_real,tf_imag,twiddle_bits,scale=1):
        Actor.Actor.__init__(self,clk,input_a,output_a,scale)
 
        self.output_b = output_b
 

src/p/y/pythia-0.8.1.11/opal/components/Registrar.py   pythia(Download)
    def __init__(self, name=None):
        if name is None:
            name = "registrar"
 
        Actor.__init__(self, name)

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