Did I find the right examples for you? yes no      Crawl my project      Python Jobs

All Samples(5)  |  Call(5)  |  Derive(0)  |  Import(0)

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/Mux.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
    muxes_inst = self.muxes #list of the muxes created
    baseclass_logic = Actor.Actor.logic(self) #logic from the baseclass
 
    return instances()

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/DivideAndConquer.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
    calls all of the behavioural methods, for conversion purposes
    """
    baseclass_logic = Actor.Actor.logic(self) #Calls the behavioural methods by calling the Base Class Actor logic method
 
    twiddle_rom_real_inst = self.rom(self.twiddle_rom_line_real,self.twiddle_rom_addr_real,self.tf_real) #Creates a rom for the real and imaginary parts of the twiddle factors

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/Unscrambler.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
    """
    index_rom_inst = self.rom(self.index_output,self.index_addr,self.index_mapping)
    baseclass_logic = Actor.Actor.logic(self)
 
    return instances()

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/HDFT.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
    calls all of the modules used in the algorithm for conversion purposes
    """
    baseclass_logic = Actor.Actor.logic(self)
 
    #DAC Logic

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/DFT.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
    #processing_logic = self.processing()
    baseclass_logic = Actor.Actor.logic(self)
 
    return instances()