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src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/Mux.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
    for i in range(len(input_values_real)):
      output_values = Actor.Actor.model(self,[input_values_real[i]],[input_values_imag[i]])
      output_values_real.append(output_values[0][0])
      output_values_imag.append(output_values[1][0])