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src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/Mux.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
    receiving_flag = self.receiving_flag
 
    baseclass_receiving_logic = Actor.Actor.receiving(self) #calling the Actor base class receiving behaviour
 
    @always(clk.posedge,reset.posedge) #Iteration logic used to point the input to the next mux when the previous data set is complete