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All Samples(9)  |  Call(5)  |  Derive(0)  |  Import(4)

        def assemble(i):
    error = "Unknown instruction"
    # Preprocess the instruction here, this will save us quite some hacks 
    # and grief later on.
    if i.base == "d":
        # special
        return [x.value for x in (i.dst_operands + i.src_operands)]
    operands = {}
    # enumerate dest operands
    p = DST1
    for operand in i.dst_operands:
        if operand.type != OP_TYPE_PRED:
            operands[p] = operand
            p += 1
        else:
            # output predicates are handled specially
            operands[PRED_OUT] = operand
    # enumerate source operands
    p = SRC1
    for operand in i.src_operands:
        operands[p] = operand
        p += 1
    # operand set, minus predication
    operands_set = set(operands.keys())
    operands_set.discard(PRED_OUT)
    # XXX handle required operand properties: flipped, 
    # predicate in/output. Now they just get ignored for unsupporting
    # instructions.
    
    for rule in rules:
        # Match rule 
        if rule[0] != i.base:
            continue
        #print rule[0]
        try:
            mods = rule[2][:]

            # Predicate destination arguments can be filtered out
            # OUT_PRED and not DSTx
            #nonpred = [o for o in i.dst_operands if o.type != OP_TYPE_PRED]
            # Evaluate arguments, make sure they are all 'touched'
            iset = set()
            for arg, type, bits in rule[3]:
                #print arg, type, bits
                try:
                    obj = operands[arg]
                except LookupError:
                    raise ValueError("Missing required argument")
                if match_type(type, obj):
                    mods += bits
                    iset.add(arg)
            # iset contains all matched arguments (excluding PRED_IN, PRED_OUT)
            # operands_set contains all arguments
            if iset != operands_set:
                # Not all arguments matched
                # we should do better error reporting and report which arguments don't match
                raise ValueError("Invalid argument types")
            # Now that mods in complete, check if required attributes are 'touched':
            #   PRED_IN, PRED_OUT, flip, invert, offset, offset_inc
            
            # Instruction matched
            # synthesize bit field, process modifiers
            inst = [0x00000000] * rule[1]
            used = [0x00000000] * rule[1]
            r_modifiers = set(i.modifiers) # remaining modifiers
            for b in mods:
                #print b
                bf, src, sub = b[0], b[1], b[2]
                bits = None
                if len(b)==4:
                    # bit filter specified
                    bits = b[3]
                if src == IMM:
                    value = sub
                elif (src >= DST1 and src <= SRC_LAST) or src == PRED_OUT:
                    # destination or source attribute
                    try:
                        obj = operands[src]
                    except LookupError:
                        #if sub == PRESENT:
                        value = 0
                        #else:
                        #    raise ValueError("Missing argument %i" % src)
                    else:
                        if sub == PRESENT:
                            value = 1
                        elif sub == VALUE:
                            value = obj.value
                        elif sub == VALUE_ALIGN:
                            value = align_shift(obj.size, obj.value)
                        elif sub == SHTYPE:
                            if obj.size == 8:
                                value = 0
                            elif obj.size == 16:
                                if obj.sign == OP_SIGN_SIGNED:
                                    value = 2
                                else:
                                    value = 1
                            elif obj.size == 32:
                                value = 3
                            else:
                                raise ValueError("Invalid shared memory operand type")
                        elif sub == OFFSET:
                            if obj.offset != None:
                                value = obj.offset
                            else:
                                value = 0 # no offset = offset reg 0
                        elif sub == OFFSET_INC:
                            value = obj.offset_inc
                        elif sub == FLIP:
                            value = obj.flip
                        elif sub == INVERT:
                            value = obj.invert
                        elif sub == CONSTSEG:
                            value = obj.indirection - OP_INDIRECTION_CONST0
                        elif sub == IS_SIGNED:
                            value = (obj.sign == OP_SIGN_SIGNED)
                        elif sub == IS_32BIT:
                            if obj.indirection == OP_INDIRECTION_NONE:
                                if obj.size == 16 and obj.source in [OP_SOURCE_REGISTER, OP_SOURCE_OUTPUT_REGISTER]:
                                    raise ValueError("Type conflict -- expected half register")
                                if obj.size == 32 and obj.source in [OP_SOURCE_HALF_REGISTER, OP_SOURCE_HALF_OUTPUT_REGISTER]:
                                    raise ValueError("Type conflict -- expected full register")
                            value = (obj.size == 32)
                        elif sub == GET_MSIZE:
                            value = _msize_rev[(obj.sign,obj.size)]
                        elif sub == IS_OUTREG: # operand is normal or output register
                            if (obj.indirection != OP_INDIRECTION_NONE or 
                               not obj.source in [OP_SOURCE_HALF_OUTPUT_REGISTER, OP_SOURCE_OUTPUT_REGISTER, OP_SOURCE_HALF_REGISTER, OP_SOURCE_REGISTER]):
                                raise ValueError("Output register operand must be register")
                            value = obj.source in [OP_SOURCE_HALF_OUTPUT_REGISTER, OP_SOURCE_OUTPUT_REGISTER]
                        elif sub == CVTI_TYPE: # conversion type
                            value = _cvti_types_rev[(obj.sign, obj.size, obj.type)]
                        else:
                            raise ValueError("Invalid sub value %i" % sub)
                elif src == MODIFIER:
                    # check for presence of modifier
                    if sub in i.modifiers:
                        value = bits
                        try:
                            r_modifiers.remove(sub)
                        except KeyError:
                            pass # multiply occurences the same modifier are allowed
                    else:
                        if bf == BF_ALWAYS:
                            # Required value is not present
                            raise ValueError("Required modifier not present")
                        continue # modifier not there, just continue with next rule
                elif src == PRED_IN:
                    if sub == CC:
                        value = i.pred_op
                    elif sub == VALUE:
                        value = i.pred
                    else:
                        raise ValueError("Invalid sub value for PRED_IN %i" % sub)
                else:
                    raise ValueError("Invalid source value")
                # in case of BF_ALWAYS, don't set anything
                if bf != BF_ALWAYS:
                    #print "%i %08x %08x" % (bf[0], bf[1], value)
                    if bits != None and src != MODIFIER:
                        # select part of the bits
                        shift = mask_to_shift(bits)
                        value = (value & bits)>>shift
                    shift = mask_to_shift(bf[1])
                    value = value << shift
                    if (value & bf[1])!=value:
                        raise ValueError("Operand does not fit")
                    if used[bf[0]] & bf[1]: # bits were already set by another modifier?
                        # if we're trying to set it to something different, this is an collision
                        if (inst[bf[0]] & bf[1]) != value: 
                            raise ValueError("Bit collision")

                    inst[bf[0]] |= value
                    used[bf[0]] |= bf[1]
                
            if len(r_modifiers):
                raise ValueError("Unknown or unsupported modifiers "+("".join(r_modifiers)))
            return inst
        except ValueError,e:
            error = e.message
            # store error, but try next rule
            # XXX cope with errors in a smarter way, as we don't always display the most
            # interesting error now
    raise CompilationError(i.line, error) # re-raise error if we didn't find any matching rule
        


src/d/e/decuda-HEAD/Instruction.py   decuda(Download)
    def assemble(self):
        from Assembler import assemble
        self.inst = assemble(self)