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src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/system_dev_testbench.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
#March 2011
from myhdl import *
import HDFT,DFT_Model,sys
 
def test_bench_hdft(hdft_inst,input_line_real,input_line_imag,input_trigger,input_enable,output_line_real,output_line_imag,output_trigger,output_enable,clk,reset,outputdata_real,outputdata_imag,testdata_real,testdata_imag):

src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/Old_HDFT_Code/hdft_performance_testbench.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
#March 2011
from myhdl import *
import sys,math,HDFT,DFT_Model
 
def Counter(clk,reset,enable,output,done,period,n):