Did I find the right examples for you? yes no      Crawl my project      Python Jobs

All Samples(1)  |  Call(1)  |  Derive(0)  |  Import(0)

src/p/y/PyVerilog-HEAD/Netlist.py   PyVerilog(Download)
                ports = conns.get(name)
                if name in mod.ports:
                    net = mod.ports.get(name)
                else:
                    #todo: add parsing code to determine width msb/lsb here