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src/m/y/MyHDL-based-FPGA-DSP-Toolflow-HEAD/Toolflow_Code/HDFT/pipeline_mux_dev_test_script.py   MyHDL-based-FPGA-DSP-Toolflow(Download)
 
clk = Signal(bool(False))
mux = Pipeline_Mux.Pipeline_Mux(clk,input_arc,output_arc,actor_scale)
 
#Simulation