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All Samples(2)  |  Call(0)  |  Derive(0)  |  Import(2)

src/p/y/PyVerilog-HEAD/verilogParse.py   PyVerilog(Download)
    while token != ';':
        if token == 'clk' or token == 'CLK' or token == 'Clk':
            import PortClk
            if width != 1:
                raise Exception("Expect clock signal " + token + " to have width=1, not " + str(width))

src/p/y/PyVerilog-HEAD/Netlist.py   PyVerilog(Download)
import Module
import PortIn
import PortOut
import PortClk
import ConfigParser