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All Samples(2)  |  Call(0)  |  Derive(0)  |  Import(2)

src/p/y/PyVerilog-HEAD/verilogParse.py   PyVerilog(Download)
def parseInput(s,l,t):
    import PortIn
    if t[0][0] != 'input':
        raise Exception("Expected input identifier")
    parsePort(s,l,t[0],PortIn.PortIn)

src/p/y/PyVerilog-HEAD/Netlist.py   PyVerilog(Download)
import Module
import PortIn
import PortOut
import PortClk
import ConfigParser