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All Samples(2)  |  Call(0)  |  Derive(0)  |  Import(2)

src/p/y/PyVerilog-HEAD/verilogParse.py   PyVerilog(Download)
def parseOutput(s,l,t):
    import PortOut
    if t[0][0] != 'output':
        raise Exception("Expected output identifier")
    parsePort(s,l,t[0],PortOut.PortOut)

src/p/y/PyVerilog-HEAD/Netlist.py   PyVerilog(Download)
import Module
import PortIn
import PortOut
import PortClk
import ConfigParser