Did I find the right examples for you? yes no

All Samples(5)  |  Call(0)  |  Derive(0)  |  Import(5)

src/s/t/stuff-HEAD/hack-myhdl/wavegen.py   stuff(Download)
import unittest
import sys
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
            elif select == SQWAVE:
                if phase_counter > (threshold << (PHASEWIDTH - N)):
                    _output.next = MASK - HALF
                else:
                    _output.next = -HALF
            else:   # NOISE
                _output.next = \
                    ((noise_register_16 ^ noise_register_13) & MASK) - HALF

src/s/t/stuff-HEAD/hack-myhdl/synth.py   stuff(Download)
from amps_filters import vca
from envgen import adsr
from config import (
    MHZ,
    AUDIO_RATE,

src/s/t/stuff-HEAD/hack-myhdl/output_stage.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    MHZ,
    N,

src/s/t/stuff-HEAD/hack-myhdl/envgen.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    PHASEWIDTH,
    N,
    def drive_qi_qf():
        if (q >> FRACTION_BITS) > MASK:
            qi.next = MASK
        else:
            qi.next = q >> FRACTION_BITS
    def combinatorial():
        latch_dq.next = (keydown1 and not keydown2) or (keydown2 and not keydown1) or lzero
        threshold.next = (qi == MASK)
        _out.next = qi
        if state == ATTACK:

src/s/t/stuff-HEAD/hack-myhdl/amps_filters.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    WHOLE,
    HALF,
 
                input_signed.next = HALF - 1
                input_unsigned.next = MASK
                clk.next = 0
                yield delay(1)
 
                input_signed.next = -HALF
                input_unsigned.next = MASK
                clk.next = 0
                yield delay(1)