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src/s/t/stuff-HEAD/hack-myhdl/wavegen.py   stuff(Download)
import unittest
import sys
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    QUARTERPHASE = 1 << (PHASEWIDTH - 2)
    THREEQUARTERPHASE = HALFPHASE + QUARTERPHASE
    TRIANGLESHIFT = (PHASEWIDTH - N) - 1
    RAMPSHIFT = PHASEWIDTH - N
 
                        (THREEQUARTERPHASE - phase_counter) >> TRIANGLESHIFT
            elif select == SQWAVE:
                if phase_counter > (threshold << (PHASEWIDTH - N)):
                    _output.next = MASK - HALF
                else:
def make_wavgen_ios():
    clk = Signal(False)
    reset = Signal(False)
    select = unsigned_bus(2)
    threshold = unsigned_bus(N)

src/s/t/stuff-HEAD/hack-myhdl/synth.py   stuff(Download)
from amps_filters import vca
from envgen import adsr
from config import (
    MHZ,
    AUDIO_RATE,
    sustain = unsigned_bus(4)
    _release = unsigned_bus(4)
    amplitude = unsigned_bus(N)
    _output = signed_bus(N)
 

src/o/b/oBB-0.6b/obb/rbf_funcs.py   oBB(Download)
 
    # load data
    from config import N, D, a, x, tl
 
    phi = lambda x: norm(dot(diag(tl),x)) ** 3
 
    z = dot(hstack((array([1]), s[0:D])),a[N:N+D+1])
 
    for i in range(0,N):
 
    # load data
    from config import N, D, a, x, tl
 
    gphi = lambda s: 3 * dot(dot(diag(tl), diag(tl)),s) * norm(dot(diag(tl),s))

src/s/t/stuff-HEAD/hack-myhdl/output_stage.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    MHZ,
    N,
 
    FRACTION_BITS = 16
    delay_1 = signed_bus(N)
    x = signed_bus(N)
    interp_step = signed_bus(N + FRACTION_BITS)
    interp_data = signed_bus(N + FRACTION_BITS)

src/s/t/stuff-HEAD/hack-myhdl/envgen.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    PHASEWIDTH,
    N,
    def choose_target():
        if state == ATTACK:
            target.next = 2 << (N + FRACTION_BITS)
        elif state == DECAY:
            # Line up the MSbit of sustain with the MSbit for target
            target.next = sustain << (N + FRACTION_BITS - 4)
    RELEASE: target = 0
    """
    q = unsigned_bus(N + FRACTION_BITS + 2)
    dq = unsigned_bus(N + FRACTION_BITS + 2)
    sign_bit = Signal(False)

src/s/t/stuff-HEAD/hack-myhdl/amps_filters.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    WHOLE,
    HALF,
    def drive_output():
        output_signed.next = (ab >> N)
 
    return (get_inputs, multiply, drive_output)
 
########
 
def make_ios():
    clk = Signal(False)
    input_signed = signed_bus(N)
def make_ios():
    clk = Signal(False)
    input_signed = signed_bus(N)
    input_unsigned = unsigned_bus(N)
    output_signed = signed_bus(N)

src/o/b/oBB-0.6b/obb/rbf_bounds.py   oBB(Download)
 
    # load data
    from config import N, D, a, x, tl, tl2
 
    # Simple function
 
    # Storage
    cml = zeros((N,D))
    cmu = zeros((N,D))
 
    # Bound for each centre
    for i in range(0,N):
        for j in range(0,D):
            for k in range(0,D):
                for p in range(0,N):
                    # Positive coefficient
                    if (a[p] > 0):