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src/s/t/stuff-HEAD/hack-myhdl/wavegen.py   stuff(Download)
import unittest
import sys
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
                phase_counter.next = phase_counter + delta_phase
 
            if select == RAMP:
                _output.next = (phase_counter - HALFPHASE) >> RAMPSHIFT
            elif select == TRIANGLE:
        yield delay(1)
        reset.next = 0
        select.next = RAMP
        delta_phase.next = DELTA_PHASE
        threshold.next = HALF