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src/s/t/stuff-HEAD/hack-myhdl/wavegen.py   stuff(Download)
import unittest
import sys
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    threshold = unsigned_bus(N)
    delta_phase = unsigned_bus(PHASEWIDTH)
    _output = signed_bus(N)
    return (clk, reset, select, threshold, delta_phase, _output)
 

src/s/t/stuff-HEAD/hack-myhdl/amps_filters.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    WHOLE,
    HALF,
def vca(clk, input_signed, input_unsigned, output_signed):
    a = signed_bus(18)
    b = unsigned_bus(18)
    ab = signed_bus(36)
 
def make_ios():
    clk = Signal(False)
    input_signed = signed_bus(N)
    input_unsigned = unsigned_bus(N)
    output_signed = signed_bus(N)

src/s/t/stuff-HEAD/hack-myhdl/output_stage.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    MHZ,
    N,
 
    FRACTION_BITS = 16
    delay_1 = signed_bus(N)
    x = signed_bus(N)
    interp_step = signed_bus(N + FRACTION_BITS)
    interp_data = signed_bus(N + FRACTION_BITS)

src/s/t/stuff-HEAD/hack-myhdl/synth.py   stuff(Download)
from amps_filters import vca
from envgen import adsr
from config import (
    MHZ,
    AUDIO_RATE,
    _release = unsigned_bus(4)
    amplitude = unsigned_bus(N)
    _output = signed_bus(N)
 
    # more bits than we really need, 18 bits would give 6.5536 seconds