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All Samples(3)  |  Call(1)  |  Derive(0)  |  Import(2)

src/s/t/stuff-HEAD/hack-myhdl/output_stage.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    MHZ,
    N,
        do_stuff,
        multiply,
        signed_to_unsigned(N, interp_result, interp_result_unsigned)
    ]
    return things

src/s/t/stuff-HEAD/hack-myhdl/synth.py   stuff(Download)
from amps_filters import vca
from envgen import adsr
from config import (
    MHZ,
    AUDIO_RATE,