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src/s/t/stuff-HEAD/hack-myhdl/wavegen.py   stuff(Download)
import unittest
import sys
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    RAMPSHIFT = PHASEWIDTH - N
 
    phase_counter = unsigned_bus(PHASEWIDTH)
    noise_register_16 = unsigned_bus(NOISEWIDTH16)
    noise_register_13 = unsigned_bus(NOISEWIDTH13)
def make_wavgen_ios():
    clk = Signal(False)
    reset = Signal(False)
    select = unsigned_bus(2)
    threshold = unsigned_bus(N)

src/s/t/stuff-HEAD/hack-myhdl/synth.py   stuff(Download)
from amps_filters import vca
from envgen import adsr
from config import (
    MHZ,
    AUDIO_RATE,
def make_fpga_ios():
    fastclk = Signal(False)
    reset = Signal(False)
    param_data = unsigned_bus(4)
    param_clk = Signal(False)
def fpga(fastclk, reset, param_data, param_clk, audio_req, audio_ack, dac_bit):
 
    aclk_counter = unsigned_bus(10)
    clk = Signal(False)
 
 
    keydown = Signal(False)
    select = unsigned_bus(2)
    attack = unsigned_bus(4)
    decay = unsigned_bus(4)

src/s/t/stuff-HEAD/hack-myhdl/envgen.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    PHASEWIDTH,
    N,
def lcounter(clk, lzero):
    lbits = unsigned_bus(LCOUNT_BITS)
 
    @always_comb
    def _output():
def state_machine(clk, keydown, threshold, state):
    _state = unsigned_bus(2)
 
    @always_comb
    def drive_outputs():
def make_sm_ios():
    clk = Signal(False)
    keydown = Signal(False)
    threshold = Signal(False)
    state = unsigned_bus(2)
    RELEASE: target = 0
    """
    q = unsigned_bus(N + FRACTION_BITS + 2)
    dq = unsigned_bus(N + FRACTION_BITS + 2)
    sign_bit = Signal(False)

src/s/t/stuff-HEAD/hack-myhdl/amps_filters.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    WHOLE,
    HALF,
def vca(clk, input_signed, input_unsigned, output_signed):
    a = signed_bus(18)
    b = unsigned_bus(18)
    ab = signed_bus(36)
 
def make_ios():
    clk = Signal(False)
    input_signed = signed_bus(N)
    input_unsigned = unsigned_bus(N)
    output_signed = signed_bus(N)

src/s/t/stuff-HEAD/hack-myhdl/output_stage.py   stuff(Download)
from myhdl import Signal, delay, Simulation, always_comb, \
    instance, intbv, bin, toVerilog, toVHDL, always, now, traceSignals
from config import (
    MHZ,
    N,
def delta_sigma_dac(fastclk, clk, reset, input_data, dac_bit):
 
    interp_result = signed_bus(N)
    interp_result_unsigned = unsigned_bus(N)
    # the input of the Xilinx multiplier is an 18-bit factor
    vc_estimate = unsigned_bus(16)
    # the output of the Xilinx multiplier is a 36-bit product
    sum_of_products = unsigned_bus(32)